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Gate-level Simulation and Extraction

Placement and routing involves placement of modules on chip area and routing interconnect between various modules. 

Physical Verification

Due to increase in signal speed, miniaturization of features, smaller chip sizes, lower power supply voltages, there has been greater interconnect signal integrity problem. Signal delay due to interconnect delay is more significant compared to gate delay. As a result more powerful automation tools are required for layout parameter extraction, timing delay and crosstalk simulation, and power analysis.

Parasitic Extraction

Accurate extraction of on-chip parasitics is crucial due to shrinking size and increasing contribution of interconnect delay. The parasitics consist of Resistance(R), Inductance(L) and Capacitance(C). Inductance is not critical for signal propagation until transmission line effect occurs. Resistance is easy to compute using algorithms like square counting and 2D finite-difference approach. Another reason for easy resistance estimation is that one has to consider only one conductor trace at a time. On the other hand capacitance extraction requires that neighborhood conductors be considered for electromagnetic coupling effect.

Automation tools for layout parameter extraction are Cadence Dracula, Diva, and Vampire, Avanti's Star-RC, and Mentor's xCalibre and ICextract for complete resistance and capacitance extraction.

Signal Integrity

Future of high speed Integrated circuit design depends on ability to understand and predict interconnect parasitic effects and behavior. Increasing switching speed and complexity of VLSI circuits are becoming crucial factor in determining reliability and performance of an electronic system.

A high level of accuracy for interconnect behavior. estimation is complex due to

  1. increase in metallization layers
  2. increasing material complexity
  3. higher operating frequencies.

Various aspects of signal integrity include:

1. Technology scale down : As technology takes dip into deep sub-micrometer range, lateral coupling effects between interconnects dominate compared to vertical coupling effects in micrometer technology. Aluminium has been used until recently to manufacture interconnects but increasing contribution of interconnects in signal propagation has forced IC manufacturers to replace it with material like copper with lower resistivity. As a result gain in propagation delay is almost twice. Technology scale down has introduced some new problems like complex resistance, 3-D capacitance and inductance.

2. Propagation delay: With decrease in size of technology interconnect delay increases.

3. CrossTalk:When two wire segments are closer to each other than a minimum threshold, they will interfere in each other's functioning. Signal on one wire may weaken due to electromagnetic effects of signal carried by other wire. This interference with each other's signal is called Crosstalk. With diminishing technology size Crosstalk is major contributor to high speed IC defects.

4. Crosstalk delay: is a major contributor to timing uncertainty. The simultaneous switching of the victim and the affecting signals may lead to a wide variety of phenomena. Among those most important is delay increase when the victim and aggressor signals switch in opposite directions, starting with victim signal followed by aggressor.

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