Verification challeges :
Biggest challenge in IC design is verification because the cost of single error is huge. Verification is both time consuming and requires large amount of resources. Types of verification tasks can be classified into two categories :
1. functional verification : check the functionality of synthesised and optimized design against golden representation of design.
2. implementation verification : Once placement and routing is over. The design is checked for functional correctness once again. Timing and power constraints are also verified.
White box verification methods involve use of formal methods for example Assertion based Verification
Assertion based verification is aimed at Digital Designers. ABV is a white-box verification technique. Unlike Simulation it is not applied on the block level once the design is complete. Assertion based verification can be applied alongside design process. In-fact assertion based verification entities reside in the HDL description of the design.
Assertions are active comments embedded with in the design. Assertions turn design specification into verification objects. Assertions can be used to :
Assertions are used to capture funcational specifications and assumptions of the design. An example below captures some possible assertions that can be embedded in the HDL description of the design. Since assertions travel with IP, they can be reused. Some examples of assertions are as follows :
Advantages of Assertion based design :
Languages Used to define assertions :
Emulator is a hardware device that can be used to emulate a piece of hardware functionality. It is commonly used as a debugging tool to test a system under development for functional correctness..
Emulation is a faster solution to verification problem. In Emulation a portion of emulatable design is synthesised and optimized. The compiled design is then loaded onto an emulator. Rest of the design is simulated by the workstations that are connected to the Emulator. Remember only the portion of the design that is being tested resides on the Emulator. Emulators are able to provide execution speed close to real time. This allows verification engineers to reduce verification time.
Emulation system typically consists of small number of large FPGAs. This provides multi-million ASIC-equivalent gate capacity. Such an emulation system comes as a seperate box. Emulation box can be connected to a collection of workstations using PCI card. The workstations are connected via emulation network architecture.
A complex IC is typically divided into number of different modules. Each module is develeped by a seperate team of designers. Each team verifies the functionality of its own module. The modules then go to an integration team which integrates all the modules and caries out verification. With emulation providing faster methods of design verification last minute changes can be incorporated in the design. This significantly reduces time to market.